1. Field of the Invention
The present invention relates to equipment for transmitting data and a method for the same, which can be applied, for example, to an optical disc drive. In the equipment and the method according to the invention, when compensating a dc level of modulating data, main and subordinate modulated data to be used for recording are provided in time division and the dc level is calculated in advance. The modulating data is generated on the basis of the calculation result. The total construction can be simplified and the circuit blocks for the transmission system can be commonly used for different systems.
2. Description of the Related Art
In a conventional optical disc drive, a dc level of modulating data is calculated in advance, and on the basis of the calculation, the dc level of the modulating data is compensated. The dc level of the modulating data can be suppressed and a recorded data can reliably be reproduced.
FIG. 7 is a block diagram showing a part of the optical disc drive disclosed in the Japanese Patent Application Laid Open no. 6-162668. In this optical disc drive 1, a modulation circuit 2 modulates data D1 to be used for recording in accordance with modulation system suitable for the recording characteristic of an optical disc and outputs. A pattern generator 3 receives output data D2 from the modulation circuit 2, and when the output data D2 is logic "1", the pattern generator 3 inverts the logical level and then outputs data D3.
An up-down counter 4 receives output data D3 from the pattern generator 3, and when the output data D3 is logic "1", the up-down counter 4 counts up the count value in each one frame of the output data D3, and when the output data D3 is the logic "0", the up-down counter 4 counts down the count value. Thereby, the up-down counter 4 detects the dc level of the output data D3 in each one frame.
A sign inverter 5 receives the count value from the up-down counter 4, inverts the sign of the count value and outputs the inverted sign of the count value. Thereby, the sign inverter 5 detects the dc level of the output data D3 when the sign of the output data D2 is inverted.
An adder 6A outputs the addition of the count value from the up-down counter 4 and an accumulated value stored in an accumulated value memory 7. An adder 6B outputs the addition of the output value from the sign inverter 5 and the accumulated value stored in the accumulated value memory 7. Here, the accumulated value memory 7 is designed to hold an accumulated value of a dc level of continuous modulating data.
An absolute value comparator 8 makes an added value from the adder 6A and an added value from the adder 6B into an absolute value of the former and an absolute value of the latter, respectively, and thereafter outputs the comparison result. A selector 9 selects the added value from the adder 6A or the added value from the adder 6B on the basis of the comparison result, and stores the selected added value in the accumulated value memory 7. Thereby, the selector 9 selects the added value from the adder 6A or the added value from the adder 6B so as to decrease the accumulated value of the dc level.
A one block shift register 11 delays the data D1 to be used for recording for the period of one frame and outputs the data. A modulation circuit 12 modulates the data D1 into the output data D2 in accordance with the same modulation system as the modulation circuit 2. A synchronization pattern switching circuit 13 switches the polarity of the output data D2 from a synchronizing signal added to the output data D2 on the basis of the comparison result of the absolute value comparator 8 and outputs the data. Here, the synchronization pattern switching circuit 13 switches the polarity of the output data D2 so as to correspond with the selecting process by the selector 9.
A pattern generator 14, processing the input data in the same manner as the pattern generator 3, inverts the logic of the output data, when the output data from the synchronizing signal pattern switching circuit 13 is the logic "1". Thereby, in the optical disc drive 1, the dc level of the output data D3 is detected by the up-down counter 4 in advance for one frame to the output data D3 from the pattern generator 14, and on the basis of this detection result, the pattern of the synchronizing signal is switched so as to reduce the dc level.
In the aforementioned construction in FIG. 7, the data D1 to be used for recording is designed to be delayed for the period of one frame by the one block shift register 11. However, the circuit scale of the one block shift register 11 made of delay circuits is apt to become large, and thereby the total construction becomes large to that extent, which is a problem.
Further, since the data D1 to be used for recording is thus delayed and processed by the one block shift register 11, it is difficult to commonly use the recording circuits in a system having a different length for one frame, which is another problem.